The present invention relates to a semiconductor device and manufacturing technology thereof, and for example, relates to a silicon carbide semiconductor device having a trench type MOS (Metal Oxide Semiconductor) gate structure and a technology effectively applicable to the manufacturing of the semiconductor device.
In Japanese Unexamined Patent Application Publication No. 2013-219161 (Patent Literature 1), described is a semiconductor device having a first conductivity type source region formed at the surface part of a well region, a trench formed in a predetermined region of the source region so as to expose at least the bottom surface at a drift layer, and a first conductivity type channel layer being the well region and being formed along the side surface of the trench. The channel layer is formed only between the drift layer and the source region, and the concentration of the first conductivity type impurities in the channel layer is homogeneous overall.
Further, in Japanese Unexamined Patent Application Publication No. 2012-099834 (Patent Literature 2), described is a MOS gate type silicon carbide semiconductor device having a silicon semiconductor layer of another conductivity type formed between a gate oxide film being in contact with the sidewall of a trench and a channel inversion layer surface. Disclosed is a technology of forming a silicon semiconductor layer of another conductivity type with an amorphous silicon layer, scanning the amorphous silicon layer with laser light in a direction not intersecting with the direction where the channel current of a MOS gate type silicon carbide semiconductor device flows, and transforming the amorphous silicon layer into polysilicon.
Further, in Japanese Unexamined Patent Application Publication No. 2008-016747 (Patent Literature 3), described is a trench MOS type silicon carbide semiconductor device having a first conductivity type drift layer, a second conductivity type base layer, and a first conductivity type source layer, those being stacked over a first conductivity type semiconductor substrate in this order, a stripe-shaped trench extending from the surface of the first conductivity type source layer and reaching the drift layer, and a second conductivity type layer formed at the bottom part of the trench. The second conductivity type layer formed at the bottom part of the trench and the second conductivity type base layer are coupled electrically conductively through a second conductivity type region formed at the sidewall surface in the trench width direction at both the ends of the stripe-shaped trench.
Further, in Japanese Unexamined Patent Application Publication No. 2006-351744 (Patent Literature 4), described is a method of manufacturing a silicon carbide semiconductor device by applying a surface treatment step of etching a semiconductor substrate surface about several nm to 0.1 μm by supplying hydrogen in a depressurized reaction furnace of a temperature of 1,500° C. or higher prior to a step of forming a gate oxide film over the silicon carbide semiconductor substrate.
Further, in Japanese Unexamined Patent Application Publication No. 2006-351743 (Patent Literature 5), described is a MOS gate type silicon carbide semiconductor device having a polysilicon gate electrode formed over the surface of a region of the other conductivity type interposed by a region of an conductivity type through a gate oxide film, and the region of the other conductivity type being in contact with the gate oxide film comprises a silicon semiconductor layer of the other conductivity type.